Due to double injection conductivity modulation LVTSCRs handle approximately 10 times the pulse power after snapback compared to Grounded Gate NMOS (GGNMOS) or NPN BJT structures of similar size. One of their main benefits is the ability to support high current densities which allows them to be made smaller than GGNMOS or BJTs with similar current handling capabilities. This also has the effect of providing lower parasitic capacitance. This makes LVTSCRs promising devices for IC protection.
However, they also suffer from drawbacks such as low holding voltage which makes them susceptible to latch-up. They also display a high resistance between the floating drain and drain contact, resulting in low saturation current under normal operation. Thus they have limited application in self-protecting applications. Also, they require a high triggering current. Further, LVTSCRs provide high voltage overshoot. This is due to an internal NMOS and NPN BJT structure and high triggering current. Some of these characteristics are better understood when considering a typical LVTSCR structure. FIG. 1 shows a dual gate LVTSCR, but the workings of the dual gate LVTSCR discussed below are applicable also to single gate structures. The following discussion of an LVTSCR also serves to define the terminology used for certain regions referred to in describing the invention in the detailed description of the invention section. The LVTSCR 100 includes a p-well 102, a p+ region 104 acting as p-well contact region (also referred to as the bulk 104), source contact region 106, a first polygate 108, a second polygate 110, a floating drain region 112, a p+ emitter contact region 114, a n+ drain contact region 116 and corresponding n-well isolation 118 of the emitter junction. The n+ floating drain 112 and p-well 102 define a blocking junction under the dual polygate 108, 110. FIG. 1 also shows a contact 130 to the bulk 104 and source contact region 106. It also shows an emitter contact 132 to the emitter contact region 114, and a drain contact 134 to the drain contact region 116.
Triggering of the structure 100 is dictated by the breakdown voltage. The first stage involves avalanche breakdown of the blocking junction. When the voltage is sufficiently high for impact ionization to occur, the internal NPN BJT (defined by n+ source contact region 106, p-well 102, and n-well 118) triggers causing forward injection of carriers into the n-well 118. This forward biases the junction between the p+ emitter contact region 114 and the n-well 118, to switch on the PNP BJT defined by p+ emitter contact region 114, n-well 118 and p-well 102, which in turn, injects positive charge carriers into the p-well. These are largely swept across to the n+ source contact region 106. The downside with this structure is that there is limited ability to control the triggering. While the gate voltage can be controlled to achieve some effect on triggering, this provides very limited control over the triggering of the structure. As a result Merrill clamps are often used. Merrill clamps, however, are highly space consuming.